Dual damascene interconnect structures are a well known choice for interconnecting semiconductor devices in an integrated circuit (IC) for high speed and reliable signal transmission, particularly as device feature sizes in ICs continue to scale down. It involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer. Forming dual damascene interconnect structures requires fewer processing steps than other methods and offers a higher yield and reliability. It is also particularly well-suited to metals such as copper (Cu) that provides a desired conductivity, but is difficult to be patterned by a plasma etching and prone to diffusing into inter-metal dielectric layers and silicon to degrade device performance. FIGS. 1A-1G are cross sectional views illustrating an exemplary dual damascene process for forming interconnect structures in a partially fabricated IC.
FIG. 1A illustrates a representative starting substrate 10 used for a dual damascene process. Substrate 10 includes a dielectric layer 13 (such as silicon dioxide or organic-containing low-k materials) with etched line patterns (trenches and vias). Dielectric layer 13 may be an inter-layer dielectric (ILD) layer on a semiconductor substrate, e.g., silicon, or an inter-metal dielectric layer (IMD) over another dielectric layer with an underlying interconnect level. Dielectric layer 13 has been inlaid with interconnect copper lines 17 that are generally formed to provide electrical coupling between conductive features in an underlying interconnect layer and in an overlying interconnect layer.
Shown in FIG. 1B, a diffusion barrier layer 19 is formed over the substrate, preventing underlying copper from diffusing into the dielectric and silicon. Next, a via dielectric layer 14 of bilayer dielectric structure 20 is deposited on diffusion barrier layer 19. This is followed by deposition of an etch-stop layer 21 on via dielectric layer 14. The process continues where trench dielectric layer 16 of bilayer dielectric structure 20 is deposited, in a similar manner to via dielectric layer 14, onto etch-stop layer 21. An antireflective layer 23 is subsequently deposited to the top of trench dielectric layer 16. Portions of trench dielectric layer 16 and via dielectric layer 14 are then etched away where the interconnect lines and vias are required, antireflective layer 23 facilitates the photolithographic process used to form the etch patterns.
Continuing in FIG. 1C, bilayer dielectric structure 20 is subjected to a photolithography and etching process to form openings for metal lines. In a well-known “Via-First” approach, first photolithography and etching processing is applied on the structure, a photoresist is coated on the structure and lithographically exposed to form a pattern of vias. The pattern of vias is then developed in the photoresist, an anisotropic etching process is then applied to form via openings 25 in the bilayer dielectrics. The etching etches through trench dielectric layer 16, etch-stop layer 21, via dielectric layer 14, diffusion barrier layer 19, and stops on substrate 10.
Shown in FIG. 1D, second photolithography and etching processing is subsequently applied on the structure; the structure is coated with a photoresist and lithographically exposed to form a pattern of trenches. The pattern of trenches is then developed in the photoresist, an anisotropic etching process is then applied to cut trench openings 27. The etching of trench openings 27 is controlled such that etch-stop layer 21 is not penetrated. As a result, trenches openings 27 are etched in trench dielectric layer 16, and are connected to the previously formed via openings 25 in via dielectric layer 14 where electrical couplings to underlying interconnect level are required.
Illustrated in FIG. 1E, via and trench openings 25 and 27 are then filled with copper 35 utilizing conventional deposition processes known to those skilled in the art, including CVD, plasma-assisted CVD, sputtering, electroplating, etc. Dual damascene structure 20 is then planarized to remove excess copper from its top surface and to provide a flat surface for the subsequent processing steps. Typically, a conformal diffusion barrier layer is deposited in the etched via and trench openings 25, 27 prior to filling with copper 35; the diffusion barrier layer prevents copper from diffusing into the silicon and the ILD and IMD layers. Suitable materials for the diffusion barrier layer include tantalum, tantalum nitride, tungsten, titanium, titanium tungsten, titanium nitride, and the like.
Alternatively, via and trench openings 25 and 27 may also be formed through a known “Trench-First” approach, where trench openings 27 are patterned and etched through first photolithography and etching processing, while via openings 25 are patterned and etched through second photolithography and etching processing, among other similar processing steps.
As the critical dimensions of semiconductor devices get smaller, generally both the patterned via and trench openings get narrower and deeper, i.e., the aspect ratio of the via and trench openings increases significantly. Also, in advanced process nodes, e.g., 45 nm and beyond, the narrowed line width of trench openings is getting close to the line width of via openings in order to accommodate the significantly increased routing requirements. The trend imposes serious challenges on the existing dual damascene structure formation approach in at least the following aspects.
First, due to the significantly increased metal line density, the via and trench pattern alignment involved in the existing dual photolithography and etch processing cycle becomes more difficult and error-prone; a slight misalignment between the via and trench patterns may result in opens and shorts in the dual damascene structure, leading to significant yield loss and reliability concerns. As an example, FIG. 1F illustrates a scenario where the trench pattern is misaligned with a via pattern, causing undesired metal bridges and opens between copper lines and vias.
Second, an increased via and trench opening aspect ratio in a dual damascene structure may deactivate an existing photolithography approach in that the photolithography processes currently used in the formation of a dual damascene structure typically require filling ashable resist deposition (ARD) materials, such as amorphous carbon (APF), in the etch openings after a first photolithography and etching process cycle, and prior to a second photolithography and etching process cycle. The increased via and trench opening aspect ratio in advanced process nodes may result in voids in unfilled or partially-filled etch openings, and undesirable surface step height, among other detrimental effects, thus significantly complicating or invalidating an existing ARD filling operation.